The present invention pertains to an output amplifier for an active pixel sensor cell array. More particularly, the invention pertains to an output amplifier for an active pixel sensor cell array, the amplifier having a two-stage design that reduces fixed pattern noise in the image data output from the array.
Charge-coupled devices (CCDs) have been the mainstay of conventional imaging circuits for converting photons incident at individual pixel sensor cells (of a pixel sensor cell array) into electrical signals indicative of the intensity of light energy incident at each cell. In general, a CCD uses a photogate to convert light energy incident at a cell into an electrical charge, and a series of electrodes to transfer the charge collected at the photogate to an output sense node.
Although CCDs have many strengths, including high sensitivity and fill-factor, CCDs also suffer from a number of weaknesses. These weaknesses include limited readout rates and dynamic range limitations, and notably, the difficulty in integrating CCDs with CMOS-based microprocessors.
To overcome the limitations of CCD-based imaging circuits, imaging circuits have been developed which use active pixel sensor cells to convert pixels of light energy into electrical signals. An active pixel sensor cell typically includes a conventional photodiode and a number of transistors which provide amplification, readout control, and reset control in addition to producing the electrical signal output from the cell.
FIG. 1 is an example of two identical CMOS active pixel sensor cells (10 and 11) having conventional design, connected along a column of an active pixel sensor cell array, and circuitry 21 for use in reading all cells connected along the column.
As shown in FIG. 1, cell 10 includes photodiode d1 (connected as shown between ground and Node 3), and reset transistor N1. Transistor N1 is an NMOS transistor whose drain is connected to a power supply node (Node 1) maintained at potential Vcc, whose source is connected to Node 3, and whose gate is connected to Node 2. The gate of transistor N1 is controlled (in a manner to be described below) by a RESET voltage supplied to Node 2.
Cell 10 also includes buffer transistor N2 and row select transistor N3, each of which is an NMOS transistor. Transistor N2 has a drain connected to Node 1, a source connected to Node 4, and a gate connected to Node 3. Transistor N3 has a drain connected to Node 4, a source connected to Node 6, and a gate connected to Node 5. The gate of transistor N3 is controlled (in a manner to be described below) by a ROW SELECT voltage supplied to Node 5.
As shown in FIG. 1, circuitry 20 includes detection and calculation circuit 21 whose input terminal is connected to Node 6. Circuit 21 includes a sense amplifier which outputs digital data indicative of light intensity incident at each selected cell along the column in response to voltages at Node 6 during a sampling period when each such cell is selected. Circuit 21 typically also implements correlated double sampling (xe2x80x9cCDSxe2x80x9d) or another post-processing method on the digital data output from the sense amplifier.
In normal operation, circuit 21 receives a sequence of voltages at Node 6 (which node is common to all cells connected along the column), with each pair of consecutive voltages being indicative of light intensity incident (during a sampling period) at a different one of the cells along the column.
Circuitry 20 also includes NMOS transistor N6 (whose drain is connected to Node 6 and whose source is connected to ground) and a current mirror (comprising current source I1 and NMOS transistors N4 and N5 connected as shown) which provides the necessary load for reading out the cells. Transistor N5 of the current mirror preferably sinks no more than a small current (from Node 6 to ground), since fixed pattern noise resulting from mismatches in the channel lengths of the buffer transistors in the cells will increase with increasing current sunk by the current mirror.
The gate of transistor N6 (at Node 8) is controlled by a Column Reset signal. Use of a column reset transistor such as transistor N6 is described in U.S. patent application Ser. No. 08/871,519 entitled xe2x80x9cActive Pixel Sensor Cell that Reduces Noise in the Photo Information Extracted from the Cell,xe2x80x9d filed on Jun. 9, 1997, naming Richard B. Merrill as inventor and assigned to the assignee of the present application.
Briefly, in operation of the FIG. 1 array, transistor N6 is used as a switch to place a defined voltage (ground potential) on Node 6 before circuit 21 reads one of the cells (e.g., cell 10). Preferably, the gate of transistor N6 is pulsed with a high level of column reset voltage xe2x80x9cCOLUMN RESETxe2x80x9d prior to each pulsing of the row select voltage ROW SELECT. By pulsing the column select voltage COLUMN RESET just prior to each pulsing of the row select voltage ROW SELECT, the voltage at Node 6 is pulled to zero (ground potential) just prior to reading of the relevant one of the cells. When the voltage on Node 6 is set to zero immediately prior to pulsing the row select voltage, resulting noise (in the data determined by circuit 21) is reduced substantially. For example, in one implementation of FIG. 1, the noise is reduced from approximately 15 mV (in the case that N6 remains xe2x80x9coffxe2x80x9d at all times) to approximately one millivolt.
Also in accordance with the teaching of U.S. patent application Ser. No. 08/871,519 entitled xe2x80x9cActive Pixel Sensor Cell that Reduces Noise in the Photo Information Extracted from the Cell,xe2x80x9d filed Jun. 9, 1997, switch transistor N6 is optionally replaced by a switch transistor whose channel terminals are connected between Node 6 and power supply Node 1, and whose gate is coupled to receive the column select voltage COLUMN RESET. By pulsing the voltage COLUMN RESET just before each pulsing of the row select voltage, the switch transistor pulls up the voltage at Node 6 to voltage Vcc just prior to reading of each cell. This technique also reduces noise in the data determined by circuit 21.
The operation of sampling (reading) each cell (e.g., cell 10) begins by briefly pulsing the gate of the cell""s reset transistor N1 with a high level of reset voltage xe2x80x9cRESET.xe2x80x9d This high level of the reset voltage (typically equal to Vcc, where Vcc is typically 5 volts) resets the voltage on photodiode d1 to an initial integration voltage to begin an image collection cycle.
Immediately after assertion of such pulse of the voltage signal xe2x80x9cRESET,xe2x80x9d the initial integration voltage on photodiode d1 (the voltage at Node 3) is Vini=VRESETxe2x88x92VTN1xe2x88x92VCLOCK, where VTN1 is the threshold voltage of transistor N1, VRESET is the high level of the voltage signal xe2x80x9cRESET,xe2x80x9d and VCLOCK represents reset noise from the pulsed reset voltage (assumed to be constant). Similarly, the initial integration voltage at Node 4 is VRESETxe2x88x92VTN1xe2x88x92VCLOCKxe2x88x92VTN2, where VTN2 is the threshold voltage of buffer transistor N2 (functioning as a source follower).
After the reset voltage has been pulsed and the voltage on photodiode d1 (the voltage at Node 3) has been reset, the gate of transistor N3 is pulsed with a high level of row select voltage signal xe2x80x9cROW SELECT.xe2x80x9d The high level of the row select voltage causes the voltage at Node 4, which represents the initial integration voltage of the cycle, to appear at Node 6. Detection and calculation circuit 21 then amplifies, digitizes, and stores the value of the initial integration voltage as it appears at Node 6.
Next, for a selected time period, photons are allowed to strike photodiode d1, thereby creating electron-hole pairs. Photodiode d1 is designed to limit recombination between the newly formed electron-hole pairs.
As a result, the photogenerated holes are attracted to the ground terminal of photodiode d1, while the photogenerated electrons are attracted to the positive terminal of photodiode d1, each additional electron reducing the voltage at Node 3. At the end of this image collection cycle, a final integration voltage will be present at Node 3. The final integration voltage is Vf=Vinixe2x88x92VS=VRESETxe2x88x92VTN1xe2x88x92VCLOCKxe2x88x92VS, where VS represents the change in voltage (at Node 3) due to the absorbed photons. Similarly, the final integration voltage at Node 4 is VRESETxe2x88x92VTN1xe2x88x92VCLOCKxe2x88x92VTN2xe2x88x92VS.
At the end of the image collection cycle, the gate of transistor N3 is again pulsed with a high level of row select voltage signal xe2x80x9cROW SELECTxe2x80x9d to cause the voltage at Node 4, which represents the final integration voltage of the cycle, to appear at Node 6. Detection and calculation circuit 21 amplifies and digitizes the value of the final integration voltage as it appears at Node 6, and generates data indicative of the number of photons that have been collected during the image collection cycle by calculating the difference (VS) between the digitized final integration voltage taken at the end of the cycle and the digitized stored initial integration voltage taken at the start of the cycle.
After the final integration voltage has been latched by detection and calculation circuit 21, the reset voltage RESET is again pulsed to reset the voltage on photodiode d1 to begin another image collection cycle.
One of the problems with active pixel sensor cells (e.g., cell 10 of FIG. 1) is that during typical operation, the reset voltage RESET and the row select voltage ROW SELECT have high levels for periods (typically about 30 msec) which are sufficiently long to introduce a substantial amount of 1/f noise into the cell. Such 1/f noise, which results from trapping and detrapping of surface charges, can be accurately modeled as variations in the threshold voltages of transistors N1, N2, and N3. Due to such noise, the number of photons which are absorbed by photodiode d1 during an image collection cycle is more properly expressed as (VRESETxe2x88x92VTN1xe2x88x92VCLOCKxe2x88x92VTN2)xe2x88x92(VRESETxe2x88x92VTN1xe2x88x92VCLOCKxe2x88x92VTN2xe2x88x92VSxe2x88x92Vxcex1), where Vxcex1 is a contribution due to variations in the threshold voltages of transistors N1, N2, and N3 due to 1/f noise. Thus, the variations in the threshold voltages of transistors N1, N2, and N3 add an error term Vxcex1 which erroneously yields VS+Vxcex1 as the value determining the number of absorbed photons, thereby limiting the accuracy of the cell.
In some applications (as explained in U.S. patent application Ser. No. 08/707,933, filed on Sep. 10, 1996, naming Richard B. Merrill and Kevin E. Brehmer as inventors and assigned to the assignee of the present application), it is desirable to choose Vcc to be substantially less than VRESET (the high level of the reset voltage RESET). For example, Vcc may be chosen to be 3.3 volts and VRESET may be chosen to be 5 volts. This forces reset transistor N1 to operate in the linear region in which the high level of the reset voltage causes N1 to pull the voltage at Node 3 up to Vini in a manner subject to reduced variation due to changes in the threshold voltage of reset transistor N1 due to 1/f noise. However, this technique does not eliminate fixed pattern noise due to systematic and random variation among the characteristics of cells of an active pixel sensor cell array.
Active pixel sensor cell arrays that use a conventional source follower amplifier in each cell (e.g., arrays of the type described with reference to FIG. 1) are subject to fixed pattern noise due to systematic and random variation between cells. Such fixed pattern noise is due to many different sources of gain variation that cannot easily be corrected with post processing techniques such as correlated double sampling. It has been proposed to implement a better amplifier within each cell (which would be less subject to such gain variation from cell to cell) by including a CMOS amplifier within each cell. Such a CMOS amplifier includes at least one PMOS transistor as a current source load for high gain (in addition to one or more NMOS transistors). Unfortunately, it is not currently possible to integrate a PMOS transistor into a single cell (of an active pixel sensor cell array) without increasing the cell size to an acceptable degree.
Conventional CCD imagers are typically subject to significantly less fixed pattern noise than are active pixel sensor cell arrays that include a conventional source follower output amplifier in each cell. It would be desirable to implement an active pixel sensor cell array that is subject to no more fixed pattern noise than a conventional CCD imager, without unacceptably increasing the cell size of such active pixel sensor cell array.
In a class of embodiments, the invention is an active pixel sensor cell array in which a two-stage amplifier amplifies the output of each cell of the array. For each column of cells of the array, one part of the two-stage amplifier for each cell is shared by all cells of the column, and another part of the two-stage amplifier for each cell is included within the cell itself. Preferably, the output amplification circuitry within each cell includes only NMOS transistors and does not include any PMOS transistor. In preferred embodiments, a differential amplifier within each cell is the primary stage of the cell""s output amplifier, and PMOS load circuitry including a secondary output amplifier stage is shared by all cells of the column. Preferably, a switchable bias circuit is provided to assert a bias voltage (to the gate of at least one transistor of the load circuitry) whose level depends on the state of a bias control signal. The bias voltage undergoes a transition which rapidly turns off each such transistor of the load circuitry (to reduce power consumption by the array) in response to a transition of the bias control signal from a first level to a second level, and the bias voltage undergoes a transition which causes each such transistor to conduct a desired bias current (needed to amplify fully the photodiode output of each cell to be read) in response to a transition of the bias control signal from the second level to the first level.
In preferred embodiments, the two-stage amplifier for each cell is an op amp, and the op amp for each cell comprises NMOS transistors (at least one of which is included in the cell itself) and at least one PMOS transistor, but no PMOS transistor is included within the cell itself. In some such preferred embodiments, at least one op amp is provided with capacitor feedback for increased gain.
Another aspect of the invention is an active pixel sensor cell including a differential amplifier (which asserts an amplified signal indicative of a sampled output voltage of the cell""s photodiode) and load circuitry coupled to the cell. The load circuitry includes a secondary amplifier stage (which further amplifies the amplified signal produced within the cell and typically includes at least one PMOS transistor). Preferably, the differential amplifier includes no PMOS transistor. Also preferably, the differential amplifier is the first stage of an op amp, and the remainder of the op amp (including optional capacitor feedback circuitry) is included in the load circuitry. Thus, the remainder of the op amp is coupled to the cell but not included within the cell itself.